The embodiments described herein relate to a semiconductor memory apparatus and, more particularly, to an input circuit of a semiconductor memory apparatus and a method of controlling the input circuit.
As shown in FIG. 1, testing equipment 1 for testing semiconductor memory apparatus operates with a channel region 2, which is divided into a high frequency channel capable of supporting high frequency, and a low frequency channel.
Often there are fewer high frequency channels than low frequency channels in the testing equipment 1. However, the high frequency channels are needed to test most conventional high speed semiconductor memory apparatus. The distinction between the high frequency channel and the low frequency channel is not absolute but relative. Thus, the actual frequency can be different according to the testing equipment. For example, if the period of an output of a signal, which can be supported in the high frequency channel, is 1 ns, it can be 2 ns in the low frequency channel.
As shown in FIG. 2, a conventional semiconductor memory apparatus 10 includes an input circuit 11 for receiving various signals, which are necessary for the operation of the semiconductor memory apparatus, through a buffer included therein. The signals necessary for the operation of the semiconductor memory apparatus can include data strobe signals ‘WDQS01’ and ‘WDQS23’ and clock signals ‘CLK’ and ‘CLKb’.
In order to operate the semiconductor memory apparatus 10 at a high speed of more than 1 Ghz, the data strobe signals ‘WDQS01’ and ‘WDQS23’ should have a period of less than 1 ns, as shown in FIG. 3. Thus, the data strobe signals ‘WDQS01’ and ‘WDQS23’ and the clock signals ‘CLK’ and ‘CLKb’ are often input to input circuit 11 through the high frequency channels of the testing equipment 1. Thus, for example, if the number of the high frequency channels of the testing equipment 1 is 128 and four signals are required per semiconductor memory apparatus being tested, then the maximum number of semiconductor memory apparatus that can be tested at one time is limited to 32.
Therefore, the number of semiconductor memory apparatus which can be tested at one time is limited in accordance with the number of the high frequency channels included in the testing equipment 1, thereby lowering testing efficiency.